When we talk about the signoff of digital IP, we are referring to the full verification of a block. Every feature listed in a device’s datasheet requires verification. Furthermore, every register ...

Formal methods constitute a suite of mathematically based techniques that are employed to specify, develop, and verify software systems with a high degree of rigour. These techniques aim to transform ...

Formal methods provide a rigorous mathematical foundation for the specification, development and verification of medical device software. This approach enhances both reliability and safety, which are ...

The EDA industry has a message for researchers in formal methods: There’s a right way and a wrong way, and if you don’t pick the right method, formal can be hard to crack. Pranav Ashar, CTO of Real ...

Carlos Rivero, associate professor in the Department of Computer Science, received $212,983 from the National Science Foundation for his project titled "Collaborative Research: FMitF: Track III: A ...

Bugs in RTL code are problematic, but a bug in an architectural specification can be catastrophic. If the bug remains undetected until post-silicon debugging, the design process essentially starts all ...

A new technical paper titled “A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level” was this year’s first place winner of Intel’s Hardware Security Academic Award ...

Recently we’ve seen some tremendous momentum around Assertion-Based Verification (ABV) methodologies and standards. These newer methods and standards have enabled design and verification engineers to ...

Formal verification, which uses mathematical analysis rather than simulation tests, has been available in commercial EDA tools for more than 20 years and in academia much longer. As with many new ...

In August 2023, the EEOC reached its first AI-bias settlement: $365,000 paid over a hiring algorithm that automatically rejected older applicants. Meanwhile, Europe’s new AI Act threatens fines of up ...