Security

Future-ready network design for physical security systems

A new free downloadable eBook, "Future-Ready Network Design for Physical Security Systems," explains in detail how physical security system network design has gone wrong and how we can fix it. In 2018 ...
Phys.org

Network isotopy: A framework to study the 3-D layouts of physical networks

The adjacency matrix of a network (left), and three different embeddings of this network in space (Right). The adjacency matrix of a network records information of the connectivity of the network. For ...
Semiconductor Engineering

Shortening Network-on-Chip Development Schedules Using Physical Awareness

Taking physical design into account as early as possible has been a consideration of chip development teams for quite some time. Still, in interactions with customers and partners, 2022 marked a sharp ...
Security

Planning a Zero-Trust Physical Security System Network

Intelligent physical security system devices—especially AI-enabled video cameras—have become high-value targets for hackers, who now deploy malware explicitly designed to infect these devices and lie ...
Electronic Design

Physically Aware Network-on-Chip Streamlines SoC Design Cycle

This video is part of TechXchange Talks. Arteris IP has released FlexNoC 5, a network-on-chip (NoC) IP configuration tool, designed to improve system-on-chip (SoC) designs and streamline the design ...
EDN

Physical Design Flow Taps Partition Layout

Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.
Electronic Design

Optimize SoC Design with a Network-on-Chip Strategy

How third-party interconnect IP saves time, lowers risk, and speeds completion. NoC is the predominant SoC interconnect strategy. NoC IP accommodates multiple interconnect protocols and data widths.