It’s the heating season here in North America and that means building operators and controls contractors will soon be scrambling to ensure their heating systems are working properly. It’s very likely ...

The SystemVerilog universal verification methodology (UVM) is an efficient way to generate tests and check results for functional verification, best used for block level IC or FPGA or other “smaller” ...

Last month, I started to explore when to use simple sequences and when to use complex sequences. Part of creating the correct sequence lies in the proper use of technology. For example, let’s look at ...