Hackaday

Pocket-sized Test Pattern Generator Helps Check Those CRTs

Nicholas Murray]’s Composite Test Pattern Generator is a beautifully-made, palm-sized tool that uses an ESP32-based ...
Semiconductor Engineering

Reducing Chip Test Costs With AI-Based Pattern Optimization

The old adage “time is money” is highly applicable to the production testing of semiconductor devices. Every second that a wafer or chip is under test means that the next part cannot yet be tested.
Electronic Design

Simulation Mismatches Can Foul Up Test-Pattern Verification

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...
Electronic Design

Using Timing Constraints For Generating At-Speed Test Patterns

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...
Semiconductor Engineering

In-System/In-Field Testing Using High-Quality Deterministic Test Patterns

The amount of electronic content in passenger cars is growing rapidly, primarily due to the integration of advanced safety features. The shift towards fully autonomous vehicles, which must comply with ...